(1) Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly to a method for fabricating an array of dynamic random access memory (DRAM) cells with zigzag-shaped stacked capacitors and a hemispherical grain (HSG) process to increase the capacitance while maintaining a high density of memory cells.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) circuits (devices) are extensively used in the electronics industry, and more particularly in the computer industry for storing data in binary form (1 and 0) as charge on a storage capacitor. These DRAM devices are made on semiconductor substrates (or wafers) and then the substrates are diced to form the individual DRAM circuits (or DRAM chips). Each DRAM circuit (chip) consists in part of an array of individual DRAM storage cells that store binary data (bits) as electrical charge on a storage capacitor. Further, the information is stored and retrieved from the storage capacitor by means of switching on or off a single access transistor (by way of word lines) in each memory cell using peripheral address circuits, while the charge is stored on the capacitor or sensed by way of bit lines and by read/write circuits formed on the periphery of the DRAM chip.
The access transistor for the DRAM device is usually a field effect transistor (FET), and the single capacitor in each cell is either formed in the semiconductor substrate as a trench capacitor, or built over the FET in the cell area as a stacked capacitor. To maintain a reasonable DRAM chip size and improved circuit performance, it is necessary to further reduce the area occupied by the individual cells on the DRAM chip. Unfortunately, as the cell size decreases, it becomes increasing more difficult to fabricate stacked or trench storage capacitors with sufficient capacitance to store the necessary charge to provide an acceptable signal-to-noise level for the read circuits (sense amplifiers) to detect. The reduced charge also requires more frequent refresh cycles that periodically restore the charge on these volatile storage cells. This increase in refresh cycles further reduces the performance (speed) of the DRAM circuit.
Since the capacitor area is limited to the cell size in order to accommodate the multitude of cells on the DRAM chip, it is necessary to explore alternative methods for increasing the capacitance without increasing the lateral area that the capacitor occupies on the substrate surface. In recent years the method of choice is to build stacked capacitors over the access transistors within each cell area, rather than forming trench capacitors which need to be etched to increasing depths in the substrate to maintain the necessary capacitance. The stacked capacitors also provide increased latitude in capacitor design and processing while reducing cell area. More specifically, the stacked capacitors can be extended in the vertical direction (third dimension) to increase the stacked capacitor area, and therefore to increase the capacitance.
Numerous methods of making DRAM circuits using stacked capacitors having crown shapes, fin shapes and the like have been reported in the literature. One method of overcoming this size problem is described by Wang et al. in U.S. Pat. No. 5,545,585. In this method of forming a fin-shaped capacitor, a node contact opening is etched in a disposable multilayer of alternate layers of doped and undoped oxides, and then the doped oxide layers are selectively etched to form a template on which is formed a fin-shaped capacitor bottom electrode. Another approach for making fin-shaped capacitors is taught by Hsue et al. in U.S. Pat. No. 5,436,186. Hsue also uses alternate layers of doped oxides as a disposable template on which to form the capacitor bottom electrodes. In U.S. Pat. No. 5,573,967, Tseng describes a method for making a fin-shaped capacitor in which an alternate polysilicon and oxide layer stack is patterned and the oxide is recessed by etching to form the fin-shaped capacitor bottom electrode. Still another method for making a fin-shaped capacitor is described by Tseng in U.S. Pat. No. 5,330,928 in which node contact openings are etched in a multilayer of alternate layers of silicon oxide and polysilicon. The polysilicon layers are then recessed to for fin-shaped capacitor bottom electrodes. Another method for making fin-shaped capacitors using multilayers of alternate layers of dissimilar conducting layers is described by Oehrlein et al. in U.S. Pat. No. 5,155,657. In this approach the inventors use alternate layers of polysilicon (Si) and polygermanium (Ge) in one embodiment and alternate layers of polysilicon and carbon (C) in a second embodiment of the invention. The multilayer is patterned leaving portions over the capacitor node contacts and an isotropic etch is used to etch selectively either layer to form a fin-shaped bottom electrode. A method for making a cup-shaped DRAM capacitor is described by Fazan in U.S. Pat. No. 5,597,756. Depressions are etched in a stacked layer of a first tetraethosiloxane (TEOS) oxide, a first silicon nitride, a second TEOS oxide, a second silicon nitride layer, and a borophosphosilicate (BPSG) oxide layer. An amorphous silicon bottom electrode is formed in the depression and hemispherical grain (HSG) polysilicon asperities are formed on the electrode to increase the capacitance.
Although there has been considerable work done to increase the capacitance area on these miniature DRAM stacked capacitors, there is still a need to further increase the capacitance in the unit DRAM cell while maintaining a simple process using self-aligning techniques to minimize the number of masking steps.